1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, in particular to a method of forming a junction region of a semiconductor device.
2. Description of the Related Prior Art
Generally, a semiconductor device has both regions of a cell region and a peripheral circuit region, in which the cell region has a high density since a plurality of devices are integrated while peripheral circuit region has a low density since some devices are disposed in spacing. Though the cell region and the peripheral circuit region have a same topology, aspect ratio of the cell region is higher than that of the peripheral circuit region. For example, when an etching process for forming a contact hole is performed, a junction region of the peripheral circuit is fully opened but a junction of the cell region is not opened due to the cell region a high integration and topology of a gate electrode.
In a conventional method, a junction region of the cell region is formed over a substrate to prevent contact defect. The conventional method will be described in conjunction with accompanying drawings.
Referring to FIG. 1A, field oxide layer 2 are formed on a semiconductor substrate 1, in which a cell region C and a peripheral region P are defined, by means of a conventional method. A gate insulation layer 3, a conductive layer 4 and a hard mask 5 are sequentially deposited on the semiconductor substrate 1 and patterned with a desired width to form gate electrodes.
Side wall spacers 6 are formed on both the side wall of the gate electrodes as shown in FIG. 1B. A silicon nitride layer 7 is then formed on the resulting structure alter forming the side wall spacers 6 and patterned to cover the peripheral region P.
As shown in FIG. 1C, doped epitaxial layers 8 are grown on the cell region C of the exposed semiconductor substrate 1 by means of a chemical vapor deposition process. Generally, the doped epitaxial layers 8 are not grown on an oxide layer and a silicon nitride layer. Hence, the doped epitaxial layers 8 are not formed on the field oxide layer 2, the hard mask 5, the side wall spacers 6 and the peripheral region P covered by the silicon nitride layer 7. The doped epitaxial layers 8 are only formed on a predetermined junction regions of the cell region C. Topology between the gate electrodes and the substrate in the cell region C is reduced by forming the epitaxial layers 8.
As shown in FIG. 1D, an impurity for a source and a drain is implanted into the substrate and a rapid thermal annealing is performed, thereby forming junction regions 9a, 9b, 9c and 9d. Since the peripheral region P is covered with a silicon nitride layer 7, the junction regions 9c and 9d are formed into thin thickness. Also, the impurity existing in the epitaxial layers 8 of cell region C is diffused into the semiconductor substrate 1 by means of the rapid thermal annealing so that the junction regions 9a and 9b are formed. Substantial junction regions of the cell region C are the junction regions 9a and 9b diffused into the substrate 1 and the epitaxial layers 8 formed on the substrate 1.
Referring to FIG. 1E, the silicon nitride layer 7 covering the semiconductor substrate 1 is removed by means a conventional method and an inter-insulation layer 10 is then formed on a resulting structure of the semiconductor substrate 1.
As described above, topology between the gate electrode and the junction region is reduced since the junction region of the cell region is formed over the substrate in the form of projection. Hence, a contact hole can be formed with easy.
However, there is a problem in that a threshold voltage of PMOS transistor, which is formed in a cell region or a peripheral region, is increased due to several times rapid thermal annealing. That is, the conventional method requires a high temperature during the growth of the epitaxial layer and the thermal process to form the junction region. As a result, threshold voltage of the PMOS transistor that is sensitive to thermal is changed.